Computer storage systems (such as optical, magnetic, and the like) record digital data onto the surface of a storage medium, which is typically in the form of a rotating magnetic or optical disk, by altering a surface characteristic of the disk. The digital data serves to modulate the operation of a write transducer (write head) which records binary sequences onto the disk in radially concentric or spiral tracks. In magnetic recording systems, for example, the digital data modulates the current in a write coil in order to record a series of magnetic flux transitions onto the surface of a magnetizable disk. And in optical recording systems, for example, the digital data may modulate the intensity of a laser beam in order to record a series of "pits" onto the surface of an optical disk. When reading this recorded data, a read transducer (read head), positioned in close proximity to the rotating disk, detects the alterations on the medium and generates a sequence of corresponding pulses in an analog read signal. These pulses are then detected and decoded by read channel circuitry in order to reproduce the digital sequence.
Detecting and decoding the pulses into a digital sequence can be performed by a simple peak detector in a conventional analog read channel or, as in more recent designs, by a discrete-time sequence detector in a sampled amplitude read channel. Discrete-time sequence detectors are preferred over simple analog pulse detectors because they compensate for intersymbol interference (ISI) and are less susceptible to channel noise. Consequently, discrete-time sequence detectors increase the capacity and reliability of the storage system.
There are several well known discrete-time sequence detection methods including discrete-time pulse detection (DPD), partial response (PR) with Viterbi detection, maximum likelihood sequence detection (MLSD), decision-feedback equalization (DFE), enhanced decision-feedback equalization (EDFE), and fixed-delay tree-search with decision-feedback (FDTS/DF).
Unlike conventional peak detection systems, sampled amplitude recording detects digital data by interpreting, at discrete-time instances, the actual value of the pulse data. To this end, the read channel comprises a sampling device for sampling the analog read signal, and a timing recovery circuit for synchronizing the samples to the baud rate (code bit rate). Before sampling the pulses, a variable gain amplifier adjusts the read signal's amplitude to a nominal value, and a low pass analog filter filters the read signal to attenuate channel and aliasing noise. After sampling, a digital equalizer equalizes the sample values according to a desired partial response, and a discrete-time sequence detector, such as a Viterbi detector, interprets the equalized sample values in context to determine a most likely sequence for the digital data (i.e., maximum likelihood sequence detection (MLSD)). MLSD takes into account the effect of ISI and channel noise in the detection algorithm, thereby decreasing the probability of a detection error. This increases the effective signal-to-noise ratio and, for a given (d,k) constraint, allows for significantly higher data density as compared to conventional analog peak detection read channels.
The application of sampled amplitude techniques to digital communication channels is well documented. See Y. Kabal and S. Pasupathy, "Partial Response Signaling", IEEE Trans. Commun. Tech., Vol. COM-23, pp.921-934, September; 1975; and Edward A. Lee and David G. Messerschmitt, "Digital Communication", Kluwer Academic Publishers, Boston, 1990; and G. D. Forney, Jr., "The Viterbi Algorithm", Proc. IEEE, Vol. 61, pp. 268-278, March 1973.
Applying sampled amplitude techniques to magnetic storage systems is also well documented. See Roy D. Cideciyan, Francois Dolivo, Walter Hirt, and Wolfgang Schott, "A PRML System for Digital Magnetic Recording", IEEE Journal on Selected Areas in Communications, Vol. 10 No. 1, January 1992, pp.38-56; and Wood et al, "Viterbi Detection of Class IV Partial Response on a Magnetic Recording Channel", IEEE Trans. Commun., Vol. Com-34, No. 5, pp. 454-461, May 1986; and Coker Et al, "Implementation of PRML in a Rigid Disk Drive", IEEE Trans. on Magnetics, Vol. 27, No. 6, November 1991; and Carley et al, "Adaptive Continous-Time Equalization Followed By FDTS/DF Sequence Detection", Digest of The Magnetic Recording Conference, Aug. 15-17, 1994, pp. C3; and Moon et al, "Constrained-Complexity Equalizer Design for Fixed Delay Tree Search with Decision Feedback", IEEE Trans. on Magnetics, Vol. 30, No. 5, September 1994; and Abbott et al, "Timing Recovery For Adaptive Decision Feedback Equalization of The Magnetic Storage Channel", Globecom'90 IEEE Global Telecommunications Conference 1990, San Diego, Calif., November 1990, pp.1794-1799; and Abbott et al, "Performance of Digital Magnetic Recording with Equalization and Offtrack Interference", IEEE Transactions on Magnetics, Vol. 27, No. 1, January 1991; and Cioffi et al, "Adaptive Equalization in Magnetic-Disk Storage Channels", IEEE Communication Magazine, February 1990; and Roger Wood, "Enhanced Decision Feedback Equalization", Intermag'90.
It is a general perception in the prior art that higher order read channels provide an increase in performance because less equalization is required to match the read signal to the desired partial response, and because higher order read channels tend to perform better at higher data densities. However, the trade-off in higher order read channels is the increase in complexity. For example, a Partial Response Class-IV (PR4) read channel, which has a transfer function of 1-D.sup.2, can be implemented simply as a pair of two-state sliding threshold detectors (see the above referenced paper entitled "A PRML System for Digital Magnetic Recording") However, a PR4 read channel exhibits a loss in performance due to the amount of equalization required to match the read signal to the PR4 response. An Extended Partial Response Class-IV (EPR4) read channel, which has a transfer function of (1-D) (1+D).sup.2, requires less equalization which results in performance gain over the PR4 read channel, as well as providing a general improvement in bit error rate at higher data densities. However, a full EPR4 detector requires a significantly more complex add-compare-select (ACS) state machine that operates according to an eight-state trellis. Still higher order read channels, such as EEPR4 with a transfer function of (1-D) (1+D).sup.3, provide even better performance at higher data densities but with the complexity increasing on orders of magnitude (e.g., a full EEPR4 trellis requires sixteen-states as shown in FIG. 6).
Another well known technique for enhancing the performance of a discrete-time sequence detector is to encode the recorded data according to a particular channel code, and then to "match" the trellis state machine to the code constraint of the channel code. This technique, referred to trellis coded modulation (TCM), enhances the distance property of the detector by "coding out" certain data sequences. For example, if the data is encoded into codewords having even parity, then a sequence detector with a trellis matched to this constraint will not allow the detection of codewords with odd parity, thereby increasing the distance between valid codewords. This increase in distance increases the effective signal-to-noise ratio without increasing the signal power, thereby allowing an increase in data density while maintaining an arbitrarily low bit error rate. However, matching the trellis state machine to a code constraint requires significantly more circuitry to implement. In the above parity code example, the number of states in the trellis would effectively double so that survivor sequences containing both even and odd parity could be saved until the detector reaches the end of a codeword. This increase in cost and complexity has prevented the wide spread use of trellis coded modulation in sampled amplitude read channels currently on the market.
The above referenced U.S. patent application entitled "Sampled Amplitude Read Channel Employing a Remod/Demod Sequence Detector Guided by an Error Syndrome" discloses a method for obtaining approximately the same distance enhancing performance of a trellis matched to a code constraint, but with a significant reduction in complexity. In that patent application, instead of matching the trellis state machine to a code constraint, the code constraint is used to generate an error syndrome for correcting the estimated binary sequence output by the sequence detector. The location and correction values of an error are determined by remodulating the detected binary sequence into an estimated sample sequence, subtracting the estimated sample sequence from the read signal sample sequence to generate a sample error sequence, and then filtering the sample error sequence with filters matched to minimum distance error events of the sequence detector. In this manner, the error syndrome generated using the code constraint indicates when an error has occurred in the detected binary sequence, and the filtered error sequence indicates the most likely location and correction value for the error. This technique approaches the performance gain provided by matching the trellis to the code constraint, but with a significant reduction in circuitry--etecting the error locations and correction values can be implemented cost effectively using a finite-impulse-response (FIR) filter and a small lookup table.
Although the above referenced patent application discloses the general idea of using an error syndrome to correct errors in the estimated binary sequence rather than match the detector's trellis to the code constraint, it does not suggest how to apply this technique to a system employing a run-length-limited (RLL) d=1 constraint. The RLL d=1 constraint is typically used in magnetic recording system to minimize the non-linear effect of partial erasure at higher data densities by increasing the minimum spacing between consecutive magnetic transitions. This is accomplished by encoding the recorded data according to a code constraint that ensures at least one "0" bit occurs between consecutive "1" bits in NRZI format.
Partial erasure is a non-linear reduction in pulse amplitude due to interference from an adjacent pulse caused by a consecutive magnetic transition. Although an RLL d=1 constraint reduces the deleterious effect of partial erasure, it is not normally employed due to the attendant reduction in code rate--a d=1 code is typically implemented at rate 2/3, whereas a d=0 code is typically implemented at rate 8/9. Instead, the write circuitry is normally used to compensate for partial erasure using a technique known as "write-precomp"--phase delaying the location of consecutive transitions by phase delaying the write clock. However, at higher data densities the effectiveness of write-precomp deteriorates to a point where the RLL d=1 constraint actually provides better performance even though there is a reduction in code rate. In other words, for an arbitrarily low bit error rate, it is possible to achieve higher user data densities with an RLL d=1 constraint as compared to an RLL d=0 constraint using write-precomp.
There is, therefore, a need to improve the performance of a discrete-time sequence detector for RLL d=1 sampled amplitude read channels, thereby achieving an increase in data density while maintaining an arbitrarily low bit error rate. Another aspect of the present invention is to employ a channel code to improve the performance of the sequence detector while avoiding the complexity of matching the detector's trellis state machine to the code constraint.